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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1-of-16 Decoder/Demultiplexer with Address Latch
High-Performance Silicon-Gate CMOS
The MC74HC4514 is identical in pinout to the MC14514B metal-gate CMOS device. The device inputs are compatible with standard CMOS outputs, with pullup resistors; they are compatible with LSTTL outputs. This device consists of a 4-bit storage latch with a Latch Enable and Chip Select input. When a low signal is applied to the Latch Enable input, the Address is stored, and decoded. When the Chip Select input is high, all sixteen outputs are forced to a low level. The Chip Select input is provided to facilitate the chip-select, demultiplexing, and cascading functions. The demultiplexing function is accomplished by using the Address inputs to select the desired device output, and then by using the Chip Select as a data input. * * * * * * Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 268 FETs or 67 Equivalent Gates
24
MC74HC4514
N SUFFIX PLASTIC PACKAGE CASE 724-03
1
24 1
DW SUFFIX SOIC PACKAGE CASE 751E-04
ORDERING INFORMATION MC74HCXXXXN MC74HCXXXXDW Plastic SOIC
PIN ASSIGNMENT
LATCH ENABLE A0 A1 Y7 Y6 Y5 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC CHIP SELECT A3 A2 Y10 Y11 Y8 Y9 Y14 Y15 Y12 Y13
LOGIC DIAGRAM
11 9 10 8 7 6 5 4 18 17 20 19 14 13 16 15
Y4 Y3 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y1 Y2 Y0 GND
A0 BINARY ADDRESS INPUTS A1 A2 A3 LATCH ENABLE
2 3 21 4-BIT STORAGE LATCH 4-TO-16 LINE DECODER
ACTIVE-HIGH OUTPUTS
1
CHIP SELECT PIN 24 = VCC PIN 12 = GND
10/95
(c) Motorola, Inc. 1995
1
REV 6
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* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
MOTOROLA
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
RECOMMENDED OPERATING CONDITIONS
MAXIMUM RATINGS*
MC74HC4514
Symbol
Vin, Vout
Symbol
Symbol
VCC
Vout
Tstg
ICC
Iout
VCC
Vin
PD
TL
VOH
tr, tf
Iin
VOL
ICC
TA
VIH
VIL
Iin
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP)
Storage Temperature
Power Dissipation in Still Air
DC Supply Current, VCC and GND Pins
DC Output Current, per Pin
DC Input Current, per Pin
DC Output Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Supply Voltage (Referenced to GND)
Input Rise and Fall Time (Figure 1)
Operating Temperature, All Package Types
DC Input Voltage, Output Voltage (Referenced to GND)
DC Supply Voltage (Referenced to GND)
Maximum Quiescent Supply Current (per Package)
Maximum Input Leakage Current
Maximum Low-Level Output Voltage
Minimum High-Level Output Voltage
Maximum Low-Level Input Voltage
Minimum High-Level Input Voltage
Parameter
Parameter
Parameter
Plastic DIP SOIC Package
Vin = VIH or VIL |Iout| 20 A
Vin = VIH or VIL |Iout| 20 A
Vin = VCC or GND Iout = 0 A
Vin = VCC or GND
Vin = VIH or VIL |Iout| |Iout|
Vin = VIH or VIL |Iout| |Iout|
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
v
v
v
v
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
Test Conditions
- 0.5 to VCC + 0.5
- 1.5 to VCC + 1.5
- 65 to + 150
- 0.5 to + 7.0
2 - 55 Min Value
v 4.0 mA v 5.2 mA
v 4.0 mA v 5.2 mA
0 0 0
0
2
50
25
20
260
750 500
+ 125
1000 500 400
VCC
Max
6.0
VCC V
6.0
6.0
4.5 6.0
2.0 4.5 6.0
4.5 6.0
2.0 4.5 6.0
2.0 4.5 6.0
2.0 4.5 6.0
Unit
Unit
mW
mA
mA
mA
_C
_C
_C
ns
V
V
V
V
V
- 55 to 25_C
0.1
1.5 3.15 4.2
0.26 0.26
3.98 5.48
0.1 0.1 0.1
1.9 4.4 5.9
0.3 0.9 1.2
8
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Guaranteed Limit
v 85_C v 125_C
High-Speed CMOS Logic Data DL129 -- Rev 6 1.0 1.5 3.15 4.2 0.33 0.33 3.84 5.34 0.1 0.1 0.1 1.9 4.4 5.9 0.3 0.9 1.2 80
v
1.0 1.5 3.15 4.2 0.40 0.40 3.70 5.20 0.1 0.1 0.1 1.9 4.4 5.9 0.3 0.9 1.2
160
v
Unit
A A V V V V
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NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). * Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
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AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol tPLH, tPHL tTLH, tTHL tPHL tPLH tPHL tPLH Cin Maximum Input Capacitance Maximum Output Transition Time, Any Output (Figures 1 and 5) Maximum Propagation Delay, Latch Enable to Output Y (Figures 3 and 5) Maximum Propagation Delay, Input A to Output Y (Figures 2 and 5) Maximum Propagation Delay, Chip Select to Output Y (Figures 1 and 5) Parameter VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -- - 55 to 25_C 175 35 30 230 46 39 175 35 30 230 46 39 175 35 30 10 75 15 13 Guaranteed Limit
High-Speed CMOS Logic Data DL129 -- Rev 6
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Symbol
CPD
tr, tf
tsu
tw
th
Power Dissipation Capacitance (Per Package)*
Maximum Input Rise and Fall Times (Figure 1)
Minimum Pulse Width, Latch Enable (Figure 3)
Minimum Hold Time, Latch Enable to Input A (Figure 4)
Minimum Setup Time, Input A to Latch Enable (Figure 4)
Parameter
3 VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 - 55 to 25_C Typical @ 25C, VCC = 5.0 V 1000 500 400 100 20 17 80 16 14 5 5 5 Guaranteed Limit 1000 500 400 100 20 17 125 25 21 220 44 37 290 58 49 220 44 37 290 58 49 220 44 37 10 95 19 16 70 5 5 5 1000 500 400 120 24 20 150 30 26 265 53 45 345 69 59 265 53 45 345 69 59 265 53 45 110 22 19 10 5 5 5
v 85_C v 125_C
v 85_C v 125_C
MC74HC4514
MOTOROLA Unit Unit pF pF ns ns ns ns ns ns ns ns
MC74HC4514
SWITCHING WAVEFORMS
tf CHIP SELECT 90% 50% 10% tPLH OUTPUT Y tTLH 90% 50% 10% tTHL tPHL tr VCC GND INPUT A tPLH OUTPUT Y 50% VALID 50% tPHL VALID VCC GND
Figure 1.
Figure 2.
tw VCC LATCH ENABLE 50% tPLH OUTPUT Y 50% 50% GND tPHL LATCH ENABLE INPUT A 50% tsu
VALID VCC GND th VCC 50% GND
Figure 3.
Figure 4.
TEST POINT OUTPUT DEVICE UNDER TEST CL*
* Includes all probe and jig capacitance
Figure 5. Test Circuit
MOTOROLA
4
High-Speed CMOS Logic Data DL129 -- Rev 6
MC74HC4514
FUNCTION TABLE
Address Inputs Latch Enable H H H H H H H H H H H H H H H H X L Chip Select L L L L L L L L L L L L L L L L H L A3 L L L L L L L L H H H H H H H H X X A2 L L L L H H H H L L L L H H H H X X A1 L L H H L L H H L L H H L L H H X X A0 L H L H L H L H L H L H L H L H X X Selected Output (High) Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 All Outputs = L Latched Data
PIN DESCRIPTIONS
ADDRESS INPUTS A0, A1, A2, A3 (Pins 2, 3, 21, 22) Address Inputs. These inputs are decoded to produce a high level on one of 16 outputs. The inputs are arranged such that A3 is the most-significant bit and A0 is the least- significant bit. The decimal equivalent of the binary input address indicates which of the 16 data outputs, Y0 - Y15, is selected. OUTPUTS Y0 - Y15 (Pins 11, 9, 10, 8, 7, 6, 5, 4, 18, 17, 20, 19, 14, 13, 16, 15) Active-High Outputs. These outputs produce a high level when selected (Latch Enable = H, Chip Select = L) and are at a low level when not selected. CONTROL INPUTS Latch Enable (Pin 1) Latch Enable Input. A low level on this input stores the data on the Address data inputs in the 4-bit latch. A high level on the Latch Enable input makes the latch transparent and allows the outputs to follow the inputs. Note that the data is latched only while the Latch Enable input is at a low level. Chip Select (Pin 23) Chip Select Input. A high on this input produces a low level on all outputs, regardless of what appears at the address or Latch Enable inputs. A low level on the Chip Select input allows the selected output to produce a high level.
TIMING DIAGRAM
INPUT A
LATCH ENABLE
CHIP SELECT
OUTPUT Y
High-Speed CMOS Logic Data DL129 -- Rev 6
5
MOTOROLA
MC74HC4514
EXPANDED LOGIC DIAGRAM
Y0 ABCD 11 Y1 ABCD 9 Y2 ABCD 10 A0 2 DATA Q Y3 ABCD 8 Y4 ABCD 7 Y5 ABCD 6 DATA Q Y6 ABCD 5 Y7 ABCD 4 Y8 ABCD 18 DATA Q Y9 ABCD 17 Y10 ABCD 20 Y11 ABCD 19 Y12 ABCD 14 LATCH 1 ENABLE LE Q Y13 ABCD 13 Y14 ABCD 16 Y15 ABCD 15 CHIP 23 SELECT
LE
Q
A1
3
LE
Q
A2
21
LE
Q
A3
22
DATA
Q
MOTOROLA
6
High-Speed CMOS Logic Data DL129 -- Rev 6
MC74HC4514
MICROPROCESSOR MEMORY DECODING
A12 A11 A10 MC146805 A9 A8
CHIP SELECT A3 A2 A1 A0 MC4514
+V
LATCH ENABLE
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15
0000-00FF 0100-01FF 0200-02FF 0300-03FF 0400-04FF 0500-05FF 0600-06FF 0700-07FF 0800-08FF 0900-09FF 0A00-0AFF 0B00-0BFF 0C00-0CFF 0D00-0DFF 0E00-0EFF 0F00-0FFF TO DEVICE SELECTS
HC04 CHIP SELECT A3 A2 A1 A0 MC4514
+V
LATCH ENABLE
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15
1000-10FF 1100-11FF 1200-12FF 1300-13FF 1400-14FF 1500-15FF 1600-16FF 1700-17FF 1800-18FF 1900-19FF 1A00-1AFF 1B00-1BFF 1C00-1CFF 1D00-1DFF 1E00-1EFF 1F00-1FFF
High-Speed CMOS Logic Data DL129 -- Rev 6
7
MOTOROLA
MC74HC4514
CODE TO CODE CONVERSION -- HEXADECIMAL TO BCD
+V A3 A2 A1 A0 MC146805 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 GND A3 A2 A1 R = 10 k HC4050 A0 HC4050 MC4511 ALL DIODES GENERAL PURPOSE GERMANIUM COMMON CATHODE LEDs
LATCH ENABLE
R=2k
CHIP SELECT
R = 2 k
MOTOROLA
8
High-Speed CMOS Logic Data DL129 -- Rev 6
MC74HC4514
OUTLINE DIMENSIONS
N SUFFIX PLASTIC PACKAGE CASE 724-03 ISSUE D
-B-
1 12
-A-
24 13
NOTES: 1. CHAMFERED CONTOUR OPTIONAL. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 4. CONTROLLING DIMENSION: INCH. DIM A B C D E F G J K L M N INCHES MIN MAX 1.230 1.265 0.250 0.270 0.145 0.175 0.015 0.020 0.050 BSC 0.040 0.060 0.100 BSC 0.007 0.012 0.110 0.140 0.300 BSC 0_ 15_ 0.020 0.040 MILLIMETERS MIN MAX 31.25 32.13 6.35 6.85 3.69 4.44 0.38 0.51 1.27 BSC 1.02 1.52 2.54 BSC 0.18 0.30 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
C -T-
SEATING PLANE
L
K E G F D
24 PL
NOTE 1
N J
24 PL
M
0.25 (0.010)
M
M
TB
M
0.25 (0.010)
TA
M
-A-
24 13
DW SUFFIX PLASTIC SOIC PACKAGE CASE 751E-04 ISSUE E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029
-B-
12X
P 0.010 (0.25)
M
B
M
1
12
24X
D 0.010 (0.25)
M
J TA
S
B
S
F R C -T-
SEATING PLANE X 45 _
M
22X
G
K
DIM A B C D F G J K M P R
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
High-Speed CMOS Logic Data DL129 -- Rev 6
CODELINE
9
*MC74HC4514/D*
MC74HC4514/D MOTOROLA

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